Qualcomm Incorporated today announced that it has reached an agreement with Alphawave IP Group plc regarding the terms and conditions of a recommended acquisition by Aqua Acquisition Sub LLC, an indirect wholly-owned subsidiary of Qualcomm Incorporated, for the entire issued and to be issued ordinary share capital of Alphawave Semi at an implied enterprise value of approximately US$2.4 billion.

The acquisition of Alphawave Semi aims to further accelerate, and provide key assets for, Qualcomm's expansion into data centers. Qualcomm Oryon CPU and Hexagon NPU processors are well positioned to meet the growing demand for high-performance, low-power computing, which is being driven by a rapid increase in AI inferencing and the transition to custom CPUs in data centers.

The news we've been waiting to share with you all is here! Bloodstained: The Scarlet Engagement is coming in 2026. Helmed by Creative Director SHUTARO and produced by IGA. Bloodstained: The Scarlet Engagement is an entirely new 2.5D side-scrolling RPG that will introduce exciting new lore, characters, gameplay and features to the Bloodstained franchise.

THE STORY
16th-century England drowns in the shadow of the Ethereal Castle and its deadly inhabitants. All attempts to fight this evil have been met with failure and death. In a desperate, final attempt, two heroes rise together against the Demon Lord Elias' reign of terror: Leonard Brandon and Alexander Kyteler. Leo is a young fighter with the Church's Black Wolves clan. Alex is a knight of the kingdom's White Stags and the lone survivor of an earlier expedition to fight Elias.

Kioxia announced its medium to long-term growth strategy and as a part of its growth strategy, the company is betting on advanced SSD technology to capture more market share. The company's most ambitious project is a breakthrough SSD that combines their XL-FLASH memory with a brand-new controller design. "We're taking our ultra-fast XL-Flash memory chips, which use single-level cells, and pairing them with a completely new controller," a company representative explained. "This combination should give us unprecedented performance for small-scale data operations. We're targeting over 10 million IOPS, and we plan to have samples ready by the second half of 2026." The company is also working closely with major GPU manufacturers to optimize performance for AI and graphics-intensive applications.

Meanwhile, Kioxia is rolling out its current generation of SSDs built on 8th generation BiCS FLASH technology. The CM9 series targets AI systems that need both blazing speed and rock-solid reliability to get the most out of expensive GPU hardware. On the other end, the LC9 series focuses on massive storage capacity, hitting 122 terabytes per drive for applications like large-scale databases that power AI inference systems.

Intel's "Nova Lake-S" desktop processors are getting the finishing touches, with a likely arrival scheduled for the second half of 2026. As the successor to "Arrow Lake Refresh," Nova Lake-S introduces a modular design that separates graphics and media functions across distinct tiles. This approach builds on experience from "Meteor Lake," which splits its graphics engine from its media and display units onto separate chiplets. For Nova Lake-S, Intel plans to employ two different GPU architectures: Xe3 "Celestial" for graphics rendering and Xe4 "Druid" for media and display duties, all within a single package. Celestial will manage primary 3D rendering and gaming workloads, while Druid will handle display pipelines and hardware-accelerated video encoding and decoding. By utilizing a more advanced process node, such as TSMC's 2 nm, Intel can optimize media engine performance without increasing costs for the entire GPU subsystem.

On the CPU side, Nova Lake-S is expected to span four primary SKU tiers. The flagship model could feature 52 cores (16 P-cores, 32 E-cores, and four LPE-cores). A 28-core version may target high-end laptops and desktops with eight P-cores, 16 E-cores, and four low-power E-cores. A 16-core variant could serve both the lower-power desktop and laptop segments, featuring four P-cores, eight E-cores, and four low-power E-cores. Finally, an 8-core entry-level part offers four P-cores and four low-power E-cores. Although it remains uncertain whether all SKUs will combine both Xe3 and Xe4 tiles, Intel's tile-based strategy makes it straightforward to mix and match GPU configurations for different market segments. Rumors also suggest that Intel may use its 18A node alongside TSMC's advanced processes for various tile elements. As Panther Lake mobile parts approach the second half of 2025 and Arrow Lake Refresh prepares for its desktop release, Nova Lake-S is the pinnacle of Intel's advanced chip packaging.

Early indications of AMD's next-generation Ryzen processors have surfaced as AIDA64's newest beta release adds initial support for Ryzen 10000 "Zen 6" desktop, server, and mobile chips. The update was noted by X user HXL, suggesting that AMD has quietly shared basic specifications with developers of hardware monitoring software. Looking back, AIDA64 tends to announce chip support almost a year before official launches, so these new processors may not appear until Computex 2026. Leaks from March 2025 suggest that AMD's Zen 6 desktop lineup, currently codenamed Medusa Ridge, will remain compatible with the existing AM5 socket. This news should please PC enthusiasts because it means many users will not have to replace their motherboards when upgrading. Reports indicate that Medusa Ridge CPUs may include 12-core chiplet dies, marking a step forward from previous architectures.

These chips are expected to be manufactured using TSMC's N3P process, which is designed to deliver improved power efficiency and higher frequencies. Additionally, a Zen 6-based X3D series is likely to feature a 3D V-Cache, targeting gamers. A model like the Ryzen 7 10800X3D could follow the success of the 9800X3D by offering strong performance at its price. On the mobile side, "Medusa Point" processors are rumored to incorporate up to 22 hybrid cores that combine performance and efficiency cores under the Zen 6 architecture. However, these mobile chips seem to be further off, with a launch window set for late 2026 or early 2027. Although AIDA64's beta edition now recognizes Ryzen 10000 series chips, AMD's usual schedule suggests we will not see them in shops until mid-2026 at the earliest. Still, compatibility with AM5 and a move to a more advanced process promise meaningful improvements when Zen 6 finally arrives.

Dell Technologies (NYSE: DELL) announces financial results for its fiscal 2026 first quarter. The company also provides guidance for its fiscal 2026-second quarter and full year.

First-Quarter Summary

• First-quarter revenue of $23.4 billion, up 5% year over year
• First-quarter operating income of $1.2 billion, up 21% year over year, and non-GAAP operating income of $1.7 billion, up 10%
• First-quarter diluted EPS of $1.37, flat year over year, and non-GAAP diluted EPS of $1.55, up 17%

After recording strong results in the first quarter of 2025, IDC is increasing its traditional PC forecast for 2025—this comes despite the significant impact that US tariffs have had on its trading partners' market sentiment. Global PC volume is now expected to reach 274 million in 2025, growing +4.1% over the prior year. Beyond 2025, IDC forecasts a slight contraction in 2026 due in part from volume stabilization following Windows 11 migration and to a more difficult comparison given a stronger market in 2025.

"The 90 day pause and tariffs exemption applied to personal computers, combined with a definite level of uncertainty on what will happen after the 90 day pause, is motivating PC manufacturers to seize the moment and ship larger than anticipated volumes in the US," said Jean Philippe Bouchard, research VP with IDC's Worldwide PC Trackers. "However, expectations of worsening macroeconomic conditions around the world and in the US characterized by upward pressures on prices and degrading consumer sentiment, will impact the PC market in the second half of 2025. Nonetheless, IDC expects commercial demand for PCs to be healthy in 2025 as the Windows 11 migration continues steadily."

NVIDIA today reported revenue for the first quarter ended April 27, 2025, of $44.1 billion, up 12% from the previous quarter and up 69% from a year ago.

On April 9, 2025, NVIDIA was informed by the U.S. government that a license is required for exports of its H20 products into the China market. As a result of these new requirements, NVIDIA incurred a $4.5 billion charge in the first quarter of fiscal 2026 associated with H20 excess inventory and purchase obligations as the demand for H20 diminished. Sales of H20 products were $4.6 billion for the first quarter of fiscal 2026 prior to the new export licensing requirements. NVIDIA was unable to ship an additional $2.5 billion of H20 revenue in the first quarter.

AMD is already looking ahead to its Zen 7 generation and is planning the final details for its next generation of Zen IP. The first hints come from YouTuber "Moore's Law Is Dead," which points to a few interesting decisions. AMD plans to extend its multi‑class core strategy that began with Zen 4c and continued into Zen 5. Zen 7 will reportedly include three types of cores: the familiar performance cores, dense cores built for maximum throughput, and a new low‑power variant aimed at energy‑efficient tasks, just like Intel and its LP/E-Cores. There is even an unspecified "PT" and "3D" core. By swapping out pipeline modules and tweaking their internal libraries, AMD can fine‑tune each core so it performs best in its intended role, from running virtual machines in the cloud to handling AI workloads at the network edge.

On the manufacturing front, Zen 7 compute chiplets (CCDs) are expected to be made on TSMC's A14 process, which will now include a backside power delivery network. This was initially slated for the N2 node but got shifted to the A16/A14 line. The 3D V‑Cache SRAM chiplets underneath the CCDs will remain on TSMC's N4 node. It is a conservative choice, since TSMC has talked up using N2‑based chiplets for stacked memory in advanced packaging, but AMD appears to be playing it safe. Cache sizes should grow, too. Each core will get 2 MB of L2 cache instead of the current 1 MB, and L3 cache per core could expand to 7 MB through stacked V‑Cache slices. Standard CCDs without V‑Cache will still have around 32 MB of shared L3. A bold rumor suggests an EPYC model could feature 33 cores per CCD, totaling 264 cores across eight CCDs. Zen 7 tape‑out is planned for late 2026 or early 2027, and we probably won't see products on shelves until 2028 or later. As always with early-stage plans, take these details with a healthy dose of skepticism. The final Zen 7 lineup could look quite different once AMD locks down its roadmap.

At the recent AI Semiconductor Forum in Seoul, Samsung Electronics revealed that it will adopt hybrid bonding in its upcoming HBM4 memory stacks. This decision is intended to reduce thermal resistance and enable an ultra‑wide memory interface, qualities that become ever more critical as artificial intelligence and high‑performance computing applications demand greater bandwidth and efficiency. Unlike current stacking methods that join DRAM dies with tiny solder microbumps and underfill materials, hybrid bonding bonds copper‑to‑copper and oxide‑to‑oxide surfaces directly, resulting in thinner, more thermally efficient 3D assemblies. High‑bandwidth memory works by stacking multiple DRAM dies on top of a base logic die, with through‑silicon vias carrying signals vertically through each layer. Traditionally, microbumps routed horizontal connections between dies, but as data rates increase and stack heights grow, these bumps introduce significant electrical and thermal limitations.

Hybrid bonding addresses those issues by allowing interconnect pitches below 10 micrometers, which lowers both resistance and capacitance and improves overall signal integrity. SK hynix has taken a different path. The company is enhancing its molded reflow underfill (MR‑MUF) process to produce 16‑Hi HBM4 stacks that comply with JEDEC's maximum height requirement of 775 micrometers. The company believes that if its advanced MR‑MUF technique can achieve performance on par with hybrid bonding, they will avoid the substantial capital investment needed for the specialized equipment that true 3D copper bonding requires. The cost and space demands of hybrid bonding equipment are significant. Specialized lithography and alignment tools occupy more clean‑room real estate, increasing capital expenditures. Samsung may mitigate some of these costs through Semes, its in‑house equipment subsidiary, but it remains uncertain whether Semes can deliver production‑ready hybrid bonding systems in time for mass production. If Samsung successfully qualifies its HBM4 stacks using hybrid bonding, which it plans to begin manufacturing in 2026, the company could gain a competitive edge over Micron and SK hynix.

In December, we reported that Intel's next‑generation Arc graphics cards, based on the Xe3 "Celestial" IP, are finished. Tom Petersen of Intel confirmed that the Xe3 IP is baked, meaning that basic media engines, Xe cores, XMX matrix engines, ray‑tracing engines, and other parts of the gaming GPU are already designed and most likely awaiting trial fabrication. Today, we learn that Intel has reached pre‑silicon validation, meaning that trial production is imminent. According to the X account @Haze2K1, which shared a snippet of Intel's milestones, a pre‑silicon hardware model of the Intel Arc Xe3 Celestial IP is being used to map out frequency and power usage in firmware. As a reminder, Intel's pre‑silicon validation platform enables OEM and IBV partners to boot and test new chip architectures months before any physical silicon is available, catching design issues much earlier in the development cycle.

Intel provides OEMs and IBVs access to a secure, cloud‑based environment that faithfully emulates hardware‑representative systems, allowing developers to validate firmware and software stacks from anywhere without the need for physical labs. Most likely, Intel is running massive emulations of hardware on FPGAs, which act as an ASIC chip—an Arc Xe3 GPU in this case. The pre‑silicon validation team is now optimizing the power‑frequency curve and the voltage in sleep, rest, and boost states, as well as their respective frequencies. With the Xe3 IP taking many forms, engineers are experimenting with every possible form factor, from mobile to discrete graphics. Additionally, data pathways depend on these frequency curves, which in turn rely on power states that allow voltage to spike up and down as the application requires. As this work is now complete, engineers are moving on to other areas for optimization, and once the silicon returns from volume production, it will be fully optimized. We expect the first trial of silicon soon, with volume production by the end of the year or in early 2026.

Intel is preparing to launch its first "Panther Lake" mobile processor later this year, but only one configuration will arrive in 2025. This SKU features four high-performance P-cores paired with eight E-cores, leaves out the lower-power efficiency cores, and packs four Xe3 GPU cores. With a 45 W TDP, it is clearly aimed at mainstream gaming laptops rather than ultralight notebooks. Panther Lake fills the gap left by "Lunar Lake" with a higher power envelope and a more performance-oriented design. Lunar Lake ranged from 17 W to 28 W, while Panther Lake's 45 W shows Intel is targeting users who need more sustained compute and graphics throughput. Rumors indicate additional Panther Lake variants will arrive in Q1 of 2026, when Intel plans to have more SKUs shipping to OEMs from volume production.

One such SKU is expected to feature 12 Xe3 GPU cores for premium thin-and-light laptops without discrete graphics. All of Panther Lake processors combine "Cougar Cove" performance cores with "Darkmont" efficiency cores, following Intel's hybrid approach introduced with "Meteor Lake". Intel's decision to stagger the rollout reflects supply chain considerations and product segmentation by power and graphics capability. Gaming laptops that can rely on integrated Xe3 graphics will welcome this 45 W chip, while other form factors may wait for next year's lower-power or ultralight 15 W models. Qualification with OEM partners should begin later this year, with laptop shipments expected by late Q4 2025. Until Intel shares more details on the rest of the Panther Lake lineup, much remains speculative.

A series of April leaks have suggested that Apple's mixed reality headset engineering team is concocting two distinct next-gen solutions. Mid-month, leakers shared alleged early shots of "Vision Air"-related connectors and external parts—hinting at a potential dark blue colorway. Combined with a selection of fairly legitimate-sounding predictions from a notorious industry watcher, so-called Vision Pro sequels are on the way. Apple's Chinese manufacturing partners are reportedly deep into mass production of crucial "Vision Pro 2" components. Mark Gurman's "Power On" newsletter has provided plenty of inside knowledge stories over the past couple of months—his latest article included a section dedicated to fresh VR/AR insights: "I reported earlier this month that Apple is full steam ahead on two new successors to the Vision Pro (2023): a lighter version at a cheaper price point, and a Mac-tethered model aimed at applications that need maximum responsiveness."

He continued: "all signs point to the lighter model arriving between the end of this year and the first half of 2026. Despite the first version selling poorly, the company isn't abandoning ship here. The main uncertainty is whether the lighter version will be considered a replacement for the Vision Pro or a cheaper alternative." In theory, Apple could test "more mainstream" gaming waters with an initial rollout of the claimed cheaper + lightweight "Vision Air" model—perhaps set to do battle with readily available rival devices; e.g. Meta's dominant Quest 3 range. A full-blown Vision Pro follow-up could launch later on in 2026—likely reserved for upper-crust customers, with an increased focus on productivity applications.

At the 2025 Shanghai Auto Show, Intel revealed its next-generation automotive system-on-chip lineup, unveiling two ambitious platforms, "Frisco Lake" and "Grizzly Lake". The company described these new designs as key steps toward fully software-driven vehicles, where much of the intelligence is handled by high-performance processors instead of dedicated hardware circuits. Intel said these chips would support advanced driver assistance and richer multimedia features. Intel's second generation Software Defined Vehicle, or SDV, Frisco Lake, is built on the upcoming "Panther Lake" architecture. The first volumes are expected in the first half of 2026, and TDP options will be among 20-65 W to meet different use cases. Intel says Frisco Lake will deliver ten times more AI performance and sixty-one percent better energy efficiency compared to the current Raptor Lake-based platform.

The new graphics block is based on the third-generation Xe architecture, known as "Celestial", replacing the older Battlemage design. Frisco Lake also supports twelve simultaneous camera inputs and up to two hundred and eighty audio channels. Linux kernel patch analysis also shows Frisco Lake cores are based on Panther Lake, confirming Intel's adaptation of its client CPUs for automotive use. Looking further ahead, Intel shared an early roadmap for its third-generation SDV platform, Grizzly Lake, which should arrive in the first half of 2027. Codenamed Monument Peak, these chips will use "Nova Lake" cores and may offer up to 32 efficiency-optimized cores along with an integrated Xe GPU capable of about seven TeraFLOPS. Additional features include support for six independent displays, twelve camera interfaces, and compliance with automotive safety standards.

TSMC today unveiled its next cutting-edge logic process technology, A14, at the Company's North America Technology Symposium. Representing a significant advancement from TSMC's industry-leading N2 process, A14 is designed to drive AI transformation forward by delivering faster computing and greater power efficiency. It is also expected to enhance smartphones by improving their on-board AI capabilities, making them even smarter. Planned to enter production in 2028, the current A14 development is progressing smoothly with yield performance ahead of schedule.

Compared with the N2 process, which is about to enter volume production later this year, A14 will offer up to 15% speed improvement at the same power, or up to 30% power reduction at the same speed, along with more than 20% increase in logic density. Leveraging the Company's experience in design-technology co-optimization for nanosheet transistor, TSMC is also evolving its TSMC NanoFlex standard cell architecture to NanoFlex Pro, enabling greater performance, power efficiency and design flexibility.

Fireshine Games is delighted to introduce Duskfade, an all-new 3D action-platformer inspired by classic platformers of times gone by, coming to the PlayStation 5 (PS5) system, Xbox Series X|S, and PC in 2026.

Embark on an unforgettable adventure as Zirian, a young workshop apprentice, as he sets out to restore time itself in a world enshrouded by eternal night. Shatter the shackles of time as you jump, swing, and slash through a vibrant clockpunk world, blending nostalgia with modern gameplay in this timeless love letter to action-platformer classics.

Rejoice, Gungeoneers! Kaliber has heard your prayers! Enter the Gungeon 2 is in active development and will be coming to PC (Steam) and Nintendo Switch 2 in 2026. You can wishlist it now, even if you don't own a PC. Enter the Gungeon 2 is a reloaded, high-caliber sequel, enhanced with a new 3D art style, new weapons, new enemies, and expanded gameplay. Battle through familiar and unknown areas of the ruined Gungeon, uncovering secrets and mastering powerful weapons while destroying legions of Gundead, previously confined to the 2D plane. Choose from an expanding roster of Gungeoneers, new and old, rescue marooned heroes, and grow stronger through powerful passive and active items, blessings, curses, and your mastery of a vast arsenal of weapons.

And seek to understand why you find yourself under assault in the Gungeon once again…We're thrilled to finally reveal Enter the Gungeon 2—you've been asking for it for so long! But please note we're still in the midst of development, so we can't share too much just yet. In the meantime, we've set up an official Discord server for Dodge Roll, and we'd love to hear your thoughts on the announcement. Join to share your feedback, get updates directly from the team, enjoy giveaways, and hang out with other Gungeoneers.

Mark Gurman—Bloomberg's resident soothsayer of Apple inside track info—has disclosed predictive outlooks for next-generation M5 chip-based MacBooks. Early last month, we experienced the launch of the Northern Californian company's M4 MacBook Air series—starting at $999; also available in a refreshing metallic blue finish. The latest iteration of Apple's signature "extra slim" notebook family arrived with decent performance figures. As per usual, press and community attention has turned to a potential successor. Gurman's (March 30) Power On newsletter posited that engineers are already working on M5-powered super slim sequels—he believes that these offerings will arrive early next year, potentially reusing the current generation's 15-inch and 13-inch fanless chassis designs.

In a mid-February predictive report, Gurman theorized that Apple was planning a major overhaul of the MacBook Pro design. A radical reimagining of the long-running notebook series—that reportedly utilizes M6 chipsets and OLED panels—is a distant prospect; perhaps later on in 2026. The Cupertino-headquartered megacorp is expected to stick with its traditional release cadence, so 2025's "M5" refresh of MacBook Pro models could trickle out by October. Insiders believe that Apple will reuse existing MacBook Pro shells—the last major redesign occurred back in 2021. According to early February reportage, mass production of the much-rumored M5 chip started at some point earlier in the year. Industry moles posit that a 3 nm (N3P) node process was on the order books, chez TSMC foundries.

Intel's freshly concluded Vision 2025 "Products Update and GTM" showcase included a segment dedicated to forthcoming Core Ultra 300 "Panther Lake" client processors. Industry watchdogs have grabbed a select few screenshots from Team Blue's broadcast from Las Vegas, Nevada—one backdropped slide confirms that Intel's next-generation mobile CPU series will launch in 2026. This information mirrors the company's Chinese office presenting of an AI PC roadmap—coverage of last month's event highlighted a scheduled first quarter 2026 "volume" arrival of "Core Ultra Next-gen Panther Lake (18A)."

Going back to early March, Intel leadership refuted online rumors of "Panther Lake" mobile CPUs being delayed into 2026, due to alleged problems encountered during the development of the Foundry service's 18A process node. An interviewed executive repeatedly insisted that his firm's brand-new series was on track for release within the second half of 2025. Fast-forward to the end of last week; Lip-Bu Tan expressed a similar outlook in a letter addressed to investors. The newly-established boss stated: "we will further enhance our (leadership) position in the second half of this year with the launch of Panther Lake, our lead product on Intel 18A, followed by Nova Lake in 2026." Industry insiders propose that the Core Ultra 300 series will become available in a very limited capacity come October, via an Early Enablement Program (EEP). Returning to this week—Jim Johnson, senior vice president of the firm's Client Computing Group, informed a watchful audience about the merits of his group's design: "I'm personally excited about Panther Lake because it combines the power efficiency of Lunar Lake, the performance of Arrow Lake, and is built to scale 18A and is on track for production later this year...Our client roadmap is the most innovative we've ever had, and we are far from done."

In a letter to customers, Micron has announced upcoming memory price increases extending through 2025 and 2026, citing persistent supply constraints coupled with accelerating demand across its product portfolio. The manufacturer points to significant demand growth in DRAM, NAND flash, and high-bandwidth memory (HBM) segments as key drivers behind the pricing strategy. The memory market is rebounding from a prolonged oversupply cycle that previously depressed revenues industry-wide. Strategic production capacity reductions implemented by major suppliers have contributed to price stabilization and subsequent increases over the past twelve months. This pricing trajectory is expected to continue as data center operators, AI deployments, and consumer electronics manufacturers compete for limited memory allocation.

In communications to channel partners, Micron emphasized AI and HPC requirements as critical factors necessitating the price adjustments. The company has requested detailed forecast submissions from partners to optimize production planning and supply chain stability during the constrained market period. With its pricing announcement, Micron disclosed a $7 billion investment in a Singapore-based HBM assembly facility. The plant will begin operations in 2026 and will focus on HBM3E, HBM4, and HBM4E production—advanced memory technologies essential for next-generation AI accelerators and high-performance computing applications from NVIDIA, AMD, Intel, and other companies. The price increases could have cascading effects across the AI and GPU sector, potentially raising costs for products ranging from consumer gaming systems to enterprise data infrastructure. We are monitoring how these adjustments will impact hardware refresh cycles and technology adoption rates as manufacturers pass incremental costs to end customers.

Russian and Belarusian semiconductor manufacturers have achieved a significant milestone in domestic chip production capabilities. In collaboration with Belarus-based Planar, the Zelenograd Nanotechnology Center (ZNTC) has developed a new lithography system supporting 350 nm process technology for 8-inch (200 mm) silicon wafers. This development represents a strategic response to Western sanctions severely restricting Russia's access to advanced semiconductor manufacturing equipment. The system employs solid-state laser technology to project circuit patterns onto photoresist-coated wafers through a photomask that defines the circuitry. After selective exposure, the photoresist undergoes chemical processing to build circuit structures. While the 350 nm node marks a critical capability for domestic semiconductor production, it sits almost three decades behind leading-edge fabrication processes in high-performance computing applications.

This technology is comparable to what powered Intel's Pentium II processors in the late 1990s. Despite this technological gap, the equipment will enable the production of various electronic components suitable for consumer electronics and certain specialized military applications where bleeding-edge performance isn't required. ZNTC has already outlined plans to develop a more advanced 130 nm lithography system by 2026 as part of a government-backed initiative to incrementally enhance domestic semiconductor capabilities. While unable to match the 3-5 nm processes currently deployed by global semiconductor leaders, this lithography system establishes a foundation for domestic chip manufacturing infrastructure, especially in the category of mature nodes. The success of this intermediate solution will likely influence government funding priorities as the country attempts to narrow the technological gap with Western semiconductor capabilities in the coming years.

TSMC is reconfiguring its US strategy after a challenging start at its Fab 21 facility near Phoenix, Arizona. The company's initial module took nearly five years to move from groundbreaking to production—far longer than the typical two-year process observed in Taiwan. Early setbacks, including labor issues, rising costs, and cultural differences, slowed progress, but these hurdles have provided valuable lessons. With a clearer understanding of the local construction environment, TSMC plans to speed up future projects. Company executives have identified reliable local contractors and addressed many bottlenecks that once hindered progress. As a result, the Taiwanese maker is gearing up to accelerate construction timelines for its upcoming modules. Notably, TSMC intends to start building its third fab—Fab 21 module 3—this year, aiming for a pace similar to that in Taiwan.

In the current phase, TSMC is finalizing equipment installations for Fab 21 module 1 while laying the groundwork for module 2. The plan is to begin trial production of advanced 3 nm-class chips at module 2 in 2026, with high-volume manufacturing expected to kick off by 2028. The accelerated schedule for module 3 is seen as a pathway to faster production of next-generation chips, including those using the N2-series and A16 process technologies. However, rapid construction is not without risks. A critical concern remains the timely procurement of essential fab tools. Leading suppliers such as ASML and Applied Materials face significant backlogs and capacity constraints, which may delay the delivery of necessary equipment. As TSMC vows to build its US capacity more swiftly, the entire supply chain is watching closely to see if these supply chain challenges can be resolved, ensuring that the company meets its ambitious production timelines while expanding its foothold in the American market.

CD Projekt RED unveiled its primary development project late last year: The Witcher IV. A pre-rendered cinematic trailer—utilizing a highly-customized Unreal Engine 5 build running on mystery NVIDIA GPU—showcased next-generation visuals. As revealed by NVIDIA in the new year, a GeForce RTX 5090 graphics card acted as the processing conduit for CD Projekt Red's fantasy featurette. Months later, company leadership has divulged a very loose timeframe for the highly-anticipated sequel's eventual launch. During a recent call with investors—exploring financial results from 2024, and future forecasts—the company expects profits to climb consistently over the next three years. As highlighted by many news reports, long-term franchise fans will need to remain patient—CD Projekt's calendar for next year seems to be free of forthcoming AAA content: "even though we do not plan to release The Witcher 4 by the end of 2026, we are still driven by this financial goal."

Given the Polish company's flagship branch kicking into a "full production" high gear phase around late 2024, a project on the (triple-A+) scale of The Witcher IV would require a long gestation period. Renewed online theories have placed a potential release window somewhere in 2027, possibly coinciding with the rollout of next-gen consoles. A noted industry soothsayer and veteran games journalist—Jason Schreier (resident at Bloomberg)—weighed in on the matter. He has dismissed many predictive reports about The Witcher IV arriving in 2026, as well as Naughty Dog's "The Heretic Prophet"—commenting on this topic, he stated: "I'm pretty sure I said they were both going to be very early teases. Neither of those games will be out next year." Piotr Nielubowicz—CD Projekt's chief financial officer—did not go into specifics during his firm's recently concluded earnings call: "we are not going to announce the precise launch date for the game yet. All we could share now to give more visibility to investors is that the game will not be launched within the time frame of the first target for the incentive program, which ends December 31, 2026."

Last week, South Korean semiconductor industry moles let slip about the development of an "Exynos 2600" mobile chipset at Samsung Electronics. This speculative flagship processor was linked to the manufacturer's (inevitable) launch of Galaxy S26 smartphone models in early 2026. Despite rumors of the firm's Foundry service making decent progress with their preparation of a cutting-edge 2 nm Gate-All-Around (GAA) node, certain critics reckon that Samsung will be forced into signing another (less than ideal) chip supply deal with Qualcomm. According to The Bell SK's latest news report, Samsung's LSI Division is working with plenty of determination—an alleged main goal being the next wave of top-end Galaxy smartphones deployed next year with in-house tech onboard.

Inside sources propose that Samsung's Exynos 2600 SoC needs to be "finished by the middle of the third quarter of this year," thus ensuring the release of in-house chip-powered Galaxy S26 devices. It is not clear whether this forecast refers to a finalized design or the start of mass production. The latest whispers regarding another proprietary next-gen mobile processor—Exynos 2500—paint a murky picture. Past leaks indicated possible avenues heading towards forthcoming Galaxy Z Flip 7 and Fold 7 smartphone models. The latest reports have linked this design to a mature 4 nm process and eventual fitting inside affordable "Galaxy Z Flip FE" Enterprise Edition SKUs. The Bell contacted one of its trusted sources—the unnamed informant observed that everything is in flux: "Exynos 2500 production plan is constantly changing...I thought it was certain, but I heard that the possibility has recently decreased slightly." Reportedly, Samsung employees have their plates full with plenty of simultaneous projects in 2025.

AMD's next-generation Zen 6-based "Medusa Point" mobile APUs will not feature RDNA 4 graphics as previously speculated, according to recent code discoveries in AMD GPUOpen Drivers on GitHub. The Device ID "GfxIp12" associated with RDNA 4 architecture has been reserved only for discrete GPUs, confirming that the current Radeon RX 9000 series will exclusively implement AMD's latest graphics architecture. Current technical documentation indicates AMD will instead extend RDNA 3.5 implementation beyond the Zen 5 portfolio while potentially positioning UDNA as the successor technology for integrated graphics.

The chiplet-based Medusa Point design will reportedly pair a single 12-core Zen 6 CCD manufactured on TSMC's 3 nm-class node with a mobile client I/O die likely built on N4P. This arrangement is significantly different from current monolithic mobile solutions. Earlier speculation indicates the Medusa Point platform may support 3D V-Cache variants, leveraging the same vertical stacking methodology employed in current Zen 5 implementations. The mobile processor's memory controllers and neural processing unit are expected to receive substantial updates. However, compatibility limitations with AMD's latest graphics features, like FSR 4 technology, remain a concern due to the absence of RDNA 4 silicon. The Zen 6-powered Medusa Point processor family is scheduled for release in 2026, targeting premium mobile computing applications with a performance profile that builds upon AMD's current Strix Halo positioning.