During Intel's Foundry Direct Connect symposium in San Jose, where Intel confirmed the ramp of the 18A node at the Arizona fab, the company also announced Intel has achieved a significant advancement in its future node development with the announcement of "turbo cell" technology for its upcoming 14A process. Now slated for production in 2027, this progress supports Intel's objective of introducing five process nodes within a four-year period. The 18A node is presently in risk production and incorporates RibbonFET gate-all-around transistors along with PowerVia, Intel's backside power-delivery architecture. Intel anticipates transitioning 18A to full-volume manufacturing later this year, thereby internalizing greater chiplet assembly work that was previously outsourced for designs such as Lunar Lake.

For the upcoming 14A process, it combines second-generation RibbonFET with PowerDirect, the company's enhanced power network. When implemented using High-NA EUV lithography, Intel projects a performance-per-watt gain of between 15 and 20 percent over the 18A process. Of particular interest is the introduction of turbo cells. These specialized standard-cell libraries enable designers to integrate both high-performance and energy-efficient cells within a single design block. Such flexibility permits precise optimization of chip speed, power consumption, and die area to meet diverse application requirements. In practical terms, turbo cells are expected to elevate peak CPU frequencies and accelerate critical GPU pathways without incurring substantial energy penalties. Intel has already distributed its PDK for the 14A node to prospective customers for feedback, with multiple partners already planning test-chip tape-outs. Complementing these advances, the company will employ advanced packaging technologies, including Foveros 3D stacking and EMIB, and a new high-bandwidth EMIB-T variant to integrate 14A and 18A dies within unified hybrid packages.

TSMC has decided not to use High-NA EUV lithography for its upcoming angstrom-era A14 node. Instead, the world's largest contract chipmaker will stick with the field-proven 0.33-NA EUV tools. Senior Vice President at TSMC, Kevin Zhang, explained that the choice reflects TSMC's ongoing focus on keeping manufacturing steps straightforward and costs under control. Zhang noted that volume production of A14 chips is slated to begin in 2028, and the company believes it can hit its performance, yield, and density targets all the way through the two-nanometer generation without the need for High-NA equipment. He pointed out that by limiting the number of mask layers from one generation to the next, TSMC can offer customers more affordable solutions without sacrificing complexity where it counts.

This strategy places TSMC in step with Intel Foundry and several DRAM producers, who have already adopted High-NA selectively for their most critical layers. High-NA EUV scanners come with a steep sticker price of $380 million, and they require higher exposure doses and tend to run at lower throughput than standard tools. IBM researchers recently confirmed that a single High-NA exposure can cost up to 2.5 times more than a low-NA shot. Yet, when you compare a four-mask low-NA flow to a single High-NA pass, total wafer costs can drop by roughly 1.7 to 2.1 times. Despite those savings in complex multi-patterning scenarios, analysts at SemiAnalysis still expect full cost parity won't arrive until around 2030. So far, Intel is the only major foundry committed to High-NA for high-volume production. It has already processed over 30,000 trial wafers on its 14A node using ASML's Twinscan EXE:5000 High-NA tool.

High‑NA EUV lithography comes with a crazy $380 million price tag, but it can actually cut overall production costs in the right situations. At the SPIE Advanced Lithography and Patterning conference in February 2025, IBM researchers in Veldhoven revealed that one high‑NA exposure runs about 2.5x the cost of a standard low‑NA shot. That seems steep, yet High‑NA's real strength shows up when it replaces complicated multi‑patterning processes. SemiAnalysis had predicted last year that High‑NA would not become cost‑effective until around 2030, largely because higher dose requirements slow down throughput on the trickiest layers. However, after reviewing IBM's new data, the firm adjusted its outlook. Their model confirms that sticking with Low‑NA double patterning for two-mask sequences remains the cheapest path.

On the other hand, once you need three or more Low‑NA masks, switching to a single High‑NA pass starts to pay off. In fact, for a four‑mask self‑aligned litho‑etch flow, High‑NA can reduce total wafer cost by roughly 1.7-2.1x compared to using Low‑NA multi‑patterning. One big reason fabs are interested is that fewer exposures mean simpler process flows. You cut down cycle time and lower the chance of overlay mistakes. Still, SemiAnalysis warns that a simpler flow does not automatically mean lower expense in every case. Looking at Intel 14A, it turns out only a few critical metal layers at the 14A node hit the sweet spot where High‑NA's higher per‑shot cost is outweighed by ditching multiple masks.

China's domestic extreme ultraviolet (EUV) lithography development is far from a distant dream. The newest system, now undergoing testing at Huawei's Dongguan facility, leverages laser-induced discharge plasma (LDP) technology, representing a potentially disruptive approach to EUV light generation. The system is scheduled for trial production in Q3 2025, with mass manufacturing targeted for 2026, potentially positioning China to break ASML's technical monopoly in advanced lithography. The LDP approach employed in the Chinese system generates 13.5 nm EUV radiation by vaporizing tin between electrodes and converting it to plasma via high-voltage discharge, where electron-ion collisions produce the required wavelength. This methodology offers several technical advantages over ASML's laser-produced plasma (LPP) technique, including simplified architecture, reduced footprint, improved energy efficiency, and potentially lower production costs.

The LPP method relies on high-energy lasers and complex FPGA-based real-time control electronics to achieve the same result. While ASML has refined its LPP-based systems over decades, the inherent efficiency advantages of the LDP approach could accelerate China's catch-up timeline in this critical semiconductor manufacturing technology. When the US imposed sanctions on EUV shipments to Chinese companies, the Chinese semiconductor development was basically limited as standard deep ultraviolet (DUV) wave lithography systems utilize 248 nm (KrF) and 193 nm (ArF) wavelengths for semiconductor patterning, with 193 nm immersion technology representing the most advanced pre-EUV production technique. These longer wavelengths contrast with EUV's 13.5 nm radiation, requiring multiple patterning techniques to achieve advanced nodes.

Intel has successfully deployed two advanced ASML High-NA Twinscan EXE:5000 EUV lithography systems at its D1 development facility near Hillsboro, Oregon, processing approximately 30,000 wafers in a single quarter. The High-NA EUV systems, each reportedly valued at $380 million, represent a substantial improvement over previous lithography tools, achieving resolution down to 8 nm with a single exposure compared to the 13.5 nm resolution of current Low-NA systems. Early operational data indicates these machines are approximately twice as reliable as previous EUV generations, addressing reliability challenges that previously hampered Intel's manufacturing progress. The ability to accomplish with a single exposure what previously required three exposures and approximately 40 processing steps has been reduced to just "single digit" processing steps.

Intel has historically been an early adopter of high-NA EUV lithography, a much more aggressive strategy than its competitors like TSMC, which manufactures its advanced silicon using low-NA EUV tools. The company plans to utilize these systems for its upcoming 14A chip manufacturing process, though no specific mass production date has been announced. While ASML classifies these Twinscan EXE:5000 systems as pre-production tools not designed for high-volume manufacturing, Intel's extensive wafer processing is more of a test bed. The early adoption provides Intel with valuable development opportunities across various High-NA EUV manufacturing aspects, including photomask glass, pellicles, and specialized chemicals that could establish future industry standards. Intel's current 18A node is utilizing Low-NA lithography tools, where Intel is only exploring High-NA with it for testing, before moving on to 14A high-volume manufacturing with High-NA EUV.

Dai Nippon Printing Co., Ltd. (DNP) has successfully achieved the fine pattern resolution required for photomasks for logic semiconductors of the beyond 2 nm (nm: 10-9 meter) generation that support Extreme Ultra-Violet (EUV) lithography, a cutting-edge process in semiconductor manufacturing.

DNP has also completed the criteria evaluation for photomasks compatible with High-Numerical Aperture, the application being considered for next-generation semiconductors beyond the 2 nm generation, and has commenced the supply of evaluation photomasks. High-NA EUV lithography makes it possible to form fine patterns on silicon wafers with a higher resolution than previously possible, and is expected to lead to the realization of high-performance, low-power semiconductors.

According to TechNews Taiwan, Intel has made significant progress in implementing ASML's cutting-edge High-NA EUV lithography technology. The company has successfully completed the assembly of its second High-NA "Twinscan EXE" EUV system at its Portland facility, as confirmed by Mark Phillips, Intel's Director of Lithography Hardware. Christophe Fouquet, CEO of ASML, highlighted that the new assembly process allows for direct installation at the customer's site, eliminating the need for disassembly and reassembly, thus saving time and resources. Phillips expressed enthusiasm about the technology, noting that the improvements offered by High-NA EUV machines have surpassed expectations compared to standard EUV systems. Given the massive $380 million price point of these High-NA systems, any savings are valuable in the process.

The rapid progress in installation and implementation of High-NA EUV technology at Intel's facilities positions the company strongly for production transition. With all necessary infrastructure in place and inspections of High-NA EUV masks already underway, Intel aims to have its Intel 14A process in mass production by 2026-2027. As Intel leads in High-NA EUV adoption, other industry giants are following suit. ASML plans to deliver High-NA EUV systems to TSMC by year-end, with rumors suggesting that TSMC's first system will possibly arrive in September. Samsung has also committed to the technology, although recent reports indicate a potential reduction in their procurement plans. Additionally, this development has sparked discussions about the future of photoresist technology, with Phillips suggesting that while Chemically Amplified Resist (CAR) is currently sufficient, future advancements may require metal oxide photoresists. This provides a small insight into Intel's future nodes.

Samsung Electronics is set to make a significant leap in semiconductor manufacturing technology with the introduction of its first High-NA 0.55 EUV lithography tool. The company plans to install the ASML Twinscan EXE:5000 system at its Hwaseong campus between Q4 2024 and Q1 2025, marking a crucial step in developing next-generation process technologies for logic and DRAM production. This move positions Samsung about a year behind Intel but ahead of rivals TSMC and SK Hynix in adopting High-NA EUV technology. The system is expected to be operational by mid-2025, primarily for research and development purposes. Samsung is not just focusing on the lithography equipment itself but is building a comprehensive ecosystem around High-NA EUV technology.

The company is collaborating with several key partners like Lasertec (developing inspection equipment for High-NA photomasks), JSR (working on advanced photoresists), Tokyo Electron (enhancing etching machines), and Synopsys (shifting to curvilinear patterns on photomasks for improved circuit precision). The High-NA EUV technology promises significant advancements in chip manufacturing. With an 8 nm resolution capability, it could make transistors about 1.7 times smaller and increase transistor density by nearly three times compared to current Low-NA EUV systems. However, the transition to High-NA EUV comes with challenges. The tools are more expensive, costing up to $380 million each, and have a smaller imaging field. Their larger size also requires chipmakers to reconsider fab layouts. Despite these hurdles, Samsung aims for commercial implementation of High-NA EUV by 2027.

ASML, the world's sole provider of extreme ultraviolet (EUV) lithography systems essential for manufacturing the most advanced chips, has revealed its roadmap for pushing semiconductor scaling even further. In a recent presentation, former ASML president Martin van den Brink announced the company's plans for a new "Hyper-NA" EUV technology that would succeed the High-NA EUV systems, which are just beginning to deploy. The Hyper-NA tools, still in early research stages, would increase the numerical aperture to 0.75 from High-NA's 0.55, enabling chips with transistor densities beyond the projected limits of High-NA in the early 2030s. This higher numerical aperture should reduce reliance on multi-patterning techniques that add complexity and cost.

Hyper-NA is bringing challenges of its own to commercialization. Key obstacles include light polarization effects that degrade imaging contrast, requiring polarization filters that reduce light throughput. Resist materials may also need to become thinner to maintain resolution. While leading EUV chipmakers like TSMC can likely extend scaling for several more nodes using multi-patterning with existing 0.33 NA EUV tools, Intel has adopted 0.55 High-NA to avoid these complexities. But Hyper-NA will likely become essential across the industry later this decade as High-NA's physical limits are reached. Beyond Hyper-NA, few alternative patterning solutions exist besides expensive multi-beam electron lithography, which lacks the throughput of EUV photolithography. To continue classical scaling, the industry may need to eventually transition to new channel materials with superior electron mobility properties compared to silicon, requiring novel deposition and etch capabilities.

Intel is revamping its foundry play, and the company is set on its goals of becoming a strong contender to rivals such as TSMC and Samsung. Under Pat Gelsinger's lead, Intel recently split (virtually, under the same company) its units into Intel Product and Intel Foundry. During the SPIE 2024 conference for optics and photonics, Anne Kelleher, Intel's senior vice president, revealed that the 14A (1.4 nm) process offers a 15% performance-per-watt improvement over the company's 18A (1.8 nanometers) process. Additionally, the enhanced 14A-E process boasts a further 5% performance boost from the regular A14 node, being a small refresh. Intel's 14A process is set to be the first to utilize High-NA extreme ultraviolet (EUV) equipment, delivering a 20% increase in transistor logic density compared to the 18A node.

The company's aggressive pursuit of next-generation processes poses a significant threat to Samsung Electronics, which currently holds the second position in the foundry market. As part of its IDM 2.0 strategy, Intel hopes to reclaim its position as a leading foundry player and surpass Samsung by 2030. The company's collaboration with American companies, such as Microsoft, further solidifies its ambitions. Intel has already secured a $15 billion chip production contract with Microsoft for its 1.8 nm 18A process. The semiconductor industry is closely monitoring Intel's progress, as the company's advancements in process technology could potentially reshape the competitive landscape. With Samsung planning to mass-produce 2 nm process products next year, the race for dominance in the foundry market is heating up.

Chipmaking manufacturing equipment giant ASML has expressed concerns about staying in the Netherlands and considering expansion into other countries due to its home country's capped possibilities. On Wednesday, ASML executives met with Netherlands Prime Minister Mark Rutte to discuss the company's growth plans. The meeting, however, failed to fully resolve ASML's concerns surrounding the country's stance on skilled foreign labor, leaving uncertainty over the tech giant's expansion in its home market. Being one of the world's largest suppliers to chipmakers, ASML has said it needs to double its operations in the following decade to meet soaring demand. However, the company is hitting roadblocks in the Netherlands, including difficulty obtaining building permits, constraints on the electrical grid, transportation bottlenecks, and a need for supporting infrastructure like hospitals, schools, and housing. A key issue is the Netherlands' ability to attract scarce foreign engineering talent, with over 40% of ASML's Dutch workforce being non-Dutch. Recent parliamentary motions to cap international students and scrap a tax break for skilled migrants have met with criticism from ASML and other tech employers.

In an effort dubbed "Operation Beethoven," the Dutch government is scrambling to address ASML's concerns and prevent the company from expanding abroad, having already seen multinationals like Shell and Unilever leave their home country in recent years. However, ASML CEO Peter Wennink said that while the company prefers to grow in the Netherlands, it can do so elsewhere if needed. The situation comes amid pressure from the US for allies like the Netherlands to tighten restrictions on China's further access to semiconductor technology. As the sole producer of extreme ultraviolet (EUV) lithography machines crucial for advanced chipmaking, like High-NA and Low-NA, ASML holds strategic importance beyond just economics. With a new right-wing Dutch government being formed, whether a compromise can be reached to ensure ASML's continued growth in the Netherlands remains to be seen. The tech giant's decision could significantly affect the Dutch economy and its position in the global chip industry.

ASML has revealed that its cutting-edge High-NA extreme ultraviolet (EUV) chipmaking tools, called High-NA Twinscan EXE, will cost around $380 million each—over twice as much as its existing Low-NA EUV lithography systems that cost about $183 million. The company has taken 10-20 initial orders from the likes of Intel and SK Hynix and plans to manufacture 20 High-NA systems annually by 2028 to meet demand. The High-NA EUV technology represents a major breakthrough, enabling an improved 8 nm imprint resolution compared to 13 nm with current Low-NA EUV tools. This allows chipmakers to produce transistors that are nearly 1.7 times smaller, translating to a threefold increase in transistor density on chips. Attaining this level of precision is critical for manufacturing sub-3 nm chips, an industry goal for 2025-2026. It also eliminates the need for complex double patterning techniques required presently.

However, superior performance comes at a cost - literally and figuratively. The hefty $380 million price tag for each High-NA system introduces financial challenges for chipmakers. Additionally, the larger High-NA tools require completely reconfiguring chip fabrication facilities. Their halved imaging field also necessitates rethinking chip designs. As a result, adoption timelines differ across companies - Intel intends to deploy High-NA EUV at an advanced 1.8 nm (18A) node, while TSMC is taking a more conservative approach, potentially implementing it only in 2030 and not rushing the use of these lithography machines, as the company's nodes are already developing well and on time. Interestingly, the installation process of ASML's High-NA Twinscan EXE 150,000-kilogram system required 250 crates, 250 engineers, and six months to complete. So, production is as equally complex as the installation and operation of this delicate machinery.

ASML's CEO, Peter Wennink, has announced that his team will be shipping out the first pilot tool (a high-NA EUV system) in its next product line before the end of this year. Reuters reports that supply chain problems have caused hold-ups along the way, but the Dutch multinational corporation is confident in delivering its next-gen opening salvo—these high numerical aperture EUV machines are large enough to warrant transportation via truck, and their per unit cost is over €300 million (~$322 million). The most demanding of chipmakers will be snapping up ASML's behemoth apparatuses in order to produce improved (i.e. smaller) chips over the next ten years.

Wennink spoke to Reuters at an industry event (that took place in Eindhoven): "A few suppliers had some difficulties in actually ramping up and also giving us the right level of technological quality, so that led to some delay. But in fact the first shipment is still this year." The CEO expects to see a growth in revenue thanks to burgeoning interest in AI-oriented silicon—new manufacturing facilities in Arizona and Taiwan are primed to adopt high-NA EUV machines in 2024. Key clients will be experimenting with these new machines (EXE:5200), before a full push into commercial production—logic chip makers have demanded that they get priority access over memory manufacturers. Intel has made declarations, in the recent past, that its foundries are first in line to receive ASML's latest and greatest tools.

Intel Corporation today announced that it has agreed to sell an approximately 20% stake in its IMS Nanofabrication GmbH ("IMS") business to Bain Capital Special Situations ("Bain Capital"), in a transaction that values IMS at approximately $4.3 billion. The transaction is expected to close in the third quarter of 2023. IMS will operate as a standalone subsidiary and will continue to be led by CEO Dr. Elmar Platzgummer.

Since inventing multi e-beam technology and introducing the first commercial multi-beam mask writer in 2015, Vienna, Austria-based IMS has been an industry leader in multi-beam mask writing for advanced technology nodes. Intel initially invested in IMS in 2009 and ultimately acquired the business in 2015. Since the acquisition, IMS has delivered a significant return on investment to Intel while growing its workforce and production capacity by four times and delivering three additional product generations.

In an interview with Bits & Chips, ASML's CTO Martin van den Brink said that he believes that we might be reaching the end of the road for current semiconductor lithography technology in the not so distant future. However, for the time being, ASML is executing on its roadmap and after EUV, the next step is high-NA or high-numerical aperture and ASML is currently planning to have its first research high-NA scanner ready for a joint R&D venture with Imec in 2023. Assuming everything goes to plan, ASML is then planning on delivering the first R&D machines to its customers in 2024, followed by deliver of the first volume production machines using high-NA sometime in 2025. Van den Brink points out that due to the current supply chain uncertainties could affect the timing, in combination with the fact that ASML has a high demand for its EUV machines and the two technologies share a lot of components.

As such, current orders are the priority and high-NA development might be put on the back burner if need be, or as Van den Brink puts it "today's meal takes priority over tomorrow's." High-NA scanners are expected to be even more power hungry than EUV machines and are as such expected to pull around two Megawatts for the various stages. The next step in the evolution of semiconductor lithography is where ASML is expecting things to get problematic, as what the company is currently calling hyper-NA is expected to be prohibitively costly to manufacture and use. If the cost of hyper-NA grows as fast as we've seen in high-NA, it will pretty much be economically unfeasible," Van den Brink said. ASML is hoping to overcome the cost issues, but for now, the company has a plan for the next decade and things could very well change during that time and remove some of the obstacles that are currently being seen.